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Discover (Random Books)

Avalon® Interface Specifications

Avalon® Interface Specifications

Intel Corporation

Questa Verification IP Data Book

Questa Verification IP Data Book

Mentor Graphics Corporation

Harmonic Balance for Nonlinear Vibration Problems

Harmonic Balance for Nonlinear Vibration Problems

0002624

微波工程

微波工程

David M. Pozar

X-Parameters

X-Parameters

DAVID E. ROOT

应用随机过程概率论模型导论 (Sheldon M.Ross) (Z-Library)

应用随机过程概率论模型导论 (Sheldon M.Ross) (Z-Library)

未知

The Method of Moments in Electromagnetics

The Method of Moments in Electromagnetics

Walton C. Gibson

untitled

untitled

未知

Harmonic balance finite element method applications in nonlinear electromagnetics and power systems (Lu, Junwei Yamada, Sotoshi Zhao, Xiaojun) (z-lib.org)

Harmonic balance finite element method applications in nonlinear ...

未知

Designing Audio Power Amplifiers (Bob Cordell) (Z-Library)

Designing Audio Power Amplifiers (Bob Cordell) (Z-Library)

未知

RFIC2 Razavi Solution

RFIC2 Razavi Solution

未知

用于OFDM+UWB系统中的中频滤波器和可变增益放大器的研究设计

用于OFDM+UWB系统中的中频滤[..]

未知

Session 35

Session 35

未知

IEEE Std 802.11ac™-2013, IEEE Standard for Information technology—Telecommunications and information exchange between systems—Local and metropolitan area networks—Specific requirements—Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications—Amendment 4: Enhancements for Very High Throughput for Operation in Bands below 6 GHz

IEEE Std 802.11ac™-2013, IEEE Standard for Information technology—Teleco[..] ...

LAN/MAN Standards Committee of the IEEE Computer Society

LDO设计小结二

LDO设计小结二

zeng zhen

基于CMOS工艺的ESD器件及全芯片防护设计

基于CMOS工艺的ESD器件及全芯[..]

PLJIE

Middlebrook Part 1

Middlebrook Part 1

mwidmer

开关电容电路 从入门到精通

开关电容电路 从入门到精通

未知

Category: and parameters of the Triple-Speed Ethernet Intel FPGA IPcore. The Triple-Speed Ethernet Intel FPGA IP core is a configurable intellectual property (IP) core that incorporates a 10/100/1000-Mbps Ethernet media access controller (MAC) and an optional 1000BASE-X/SGMII physical coding sublayer (PCS) with an embedded PMA built with either on-chip transceiver I/Os or LVDS I/Os.

Triple-Speed Ethernet Intel® FPGA IP User Guide

Triple-Speed Ethernet Intel® FPGA IP User Guide

Intel Corporation

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