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模拟集成电路

模拟集成电路

Robust Design of LV/LP Low-Distortion CMOS Rail-to-Rail Input Stages

Robust Design of LV/LP Low-Distortion CMOS Rail-to-Rail Input ...

IEEE Std 802.11g-2003 [Amendment to IEEE Std 802.11, 1999 Edition (Reaff 2003) as amended by IEEE Stds 802.11a-1999, 802.11b-1999, 802.11b-1999/Cor 1-2001, and 802.11d-2001], Amendment 4: Further Higher Data Rate Extension in the 2.4 GHz Band

IEEE Std 802.11g-2003 [Amendment to IEEE Std 802.11, 1999 Edition ...

LAN/MAN Standards Committee of the IEEE Computer Society

Perl实例精解(原书第4版)

Perl实例精解(原书第4版)

CMOS集成电路中静电防护电路的设计与研究

CMOS集成电路中静电防护电路的设[..]

SSReader Print.

SSReader Print.

IP3 and Intermodulation Guide | Maxim Integrated

IP3 and Intermodulation Guide | Maxim Integrated

MATLAB数字信号处理85个实用案例精讲.入门到进阶

MATLAB数字信号处理85个实用[..]

Cadence SKILL Lan guage Reference

Cadence SKILL Lan guage Reference

Inc. Cadence Design Sys tems

DIFFERENTIAL EQUATIONS WITH APPLICATIONS AND HISTORICAL NOTES

DIFFERENTIAL EQUATIONS WITH APPLICATIONS AND HISTORICAL NOTES

George F. Simmons

一种用于LDO的低功耗带隙基准电压源

一种用于LDO的低功耗带隙基准电压源

一种自适应补偿的宽输入LDO设计

一种自适应补偿的宽输入LDO设计

开关电容电路从入门到精通 -刘明亮

开关电容电路从入门到精通 -刘明亮

Session 24

Session 24

Diva Reference

Diva Reference

Inc. Cadence Design Sys tems

Session 30: Non-Volatile Memories

Session 30: Non-Volatile Memories

拉扎维数据转换器设计原版 (1)

拉扎维数据转换器设计原版 (1)

$Wideband RF PLL fractional/integer frequency synthesizer with integrated VCOs and LDOs$

Wideband RF PLL fractional/integer frequency synthesizer with ...

STMICROELECTRONICS

Category: A-7

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP Product Guide (PG055)

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...

AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)

AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)

Xilinx PG153 LogiCORE IP AXI Quad Serial Peripheral Interface (SPI) v3.1, Product Guide

Xilinx PG153 LogiCORE IP AXI Quad Serial Peripheral Interface ...