A 0.46ps RJ<inf>rms</inf> 5GHz wideband LC PLL for multi-protocol ...
Chethan Rao & Shaishav Desai & Alvin Wang
LDO设计小结一
zeng zhen
CMOS模拟IP线性集成电路 (1)
未知
开关电容电路 从入门到精通
Practical RF Circuit Design for Modern Wireless Systems_ Passive ...
Name
Session 1: Plenary Session — Invited Papers
Quantus Techgen Reference Manual
计算电磁场的矩量法（PDF）
光通信集成电路设计第2版中文——拉扎维
X-Parameters
DAVID E. ROOT
Microsoft PowerPoint - PLLnoise_jitter02[..] [相容模式]
cwhsu
Static Timing Analysis final
[集成电路掩膜板设计].IC.Ma[..]
A Single-Trim CMOS Bandgap Reference With aInaccuracy of0.15% ...
Guang Ge & Cheng Zhang & Gian Hoogzaad & Kofi A. A. Makinwa
BSIM4 AND MOSFET MODELING FOR IC SIMULATION
Hu, Chenming, Liu, Weidong
一种快速瞬态响应的无片外电容LDO[..]
模拟CMOS集成电路设计 答案(拉扎维)
Session 11: Advanced Wireline Links and Techniques
PCI Express PHY v1.0 LogiCORE IP Product Guide
Xilinx, Inc.
Vivado Design Suite User Guide: Logic Simulation (UG900)
AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...
AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)
JESD204 v7.2 LogiCORE IP Product Guide (PG066)
Xilinx PG153 LogiCORE IP AXI Quad Serial Peripheral Interface ...