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CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator

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Analysis and Design of Analog Integrated Circuits, 5th Edition

Analysis and Design of Analog Integrated Circuits, 5th Edition

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模拟CMOS集成电路设计拉扎维第1版中文

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Category: This core implements a JESD204B interface supporting a line rate of up to 12.5 Gb/s on 1- 12 lanes using GTX or GTH transceivers in Zynq-7000 AP SoC devices

JESD204 v7.2 LogiCORE IP Product Guide (PG066)

JESD204 v7.2 LogiCORE IP Product Guide (PG066)