理工书库 lilin | Category: This core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.

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Session 18

Session 18

Kendall Su, Analog Filters, 2nd Ed.

Kendall Su, Analog Filters, 2nd Ed.

线性代数教材(同济五版+学习辅导与习题全解)

线性代数教材(同济五版+学习辅导与[..]

1.5Bit 级pipelined+ADC典型单级电路结构实现研究

1.5Bit 级pipelined+ADC典型单[..]

通信原理第7版

通信原理第7版

樊昌信，曹丽娜编著

高PSRR无电容型线性稳压器的研究与设计

高PSRR无电容型线性稳压器的研究与设计

Digitally-assisted design of data converters

Digitally-assisted design of data converters

Avalon Verification IP Suite User Guide

Avalon Verification IP Suite User Guide

Altera Corporation

[集成电路掩膜板设计].IC.Mask.Design

[集成电路掩膜板设计].IC.Ma[..]

模拟IC设计

模拟IC设计

Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation

Design Procedures for Three-Stage CMOS OTAs With Nested-Miller ...

Generate ESD Source in ADS

Generate ESD Source in ADS

TU,NASH (K-Taiwan,ex1)

Microelectronic circuits 6th edition

Microelectronic circuits 6th edition

ISSCC 2019 Digest of Technical Papers

ISSCC 2019 Digest of Technical Papers

ISSCC2021-T12-compressed

ISSCC2021-T12-com[..]

Session 32

Session 32

数字电子技术基础

数字电子技术基础

深入理解LINUX网络技术内幕

深入理解LINUX网络技术内幕

Category: This core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.

AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)

AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)