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Parallel Sparse Direct Solver for Integrated Circuit Simulation by Xiaoming Chen, Yu Wang, Huazhong Yang (z-lib.org)

Parallel Sparse Direct Solver for Integrated Circuit Simulation ...

多采样率系统：采样率转换和数字滤波器组

多采样率系统：采样率转换和数字滤波器组

Presentation

Presentation

Introduction to RF Power Amplifier Design and Simulation (Abdullah E.) (Z-Library)

Introduction to RF Power Amplifier Design and Simulation (Abdullah ...

Design of Sigma-Delta Converters in MATLAB

Design of Sigma-Delta Converters in MATLAB

Session 35

Session 35

a-new-semiconductor-voltage-standard

a-new-semiconduct[..]

Systematic Design of Analog CMOS Circuits

Systematic Design of Analog CMOS Circuits

Wishbone B4

Wishbone B4

Keliu Shu-2005 CMOS PLL Synthesizers Analysis and Design

Keliu Shu-2005 CMOS PLL Synthesizers Analysis and Design

IEEE Standard for Information Technology—Telecommunications and information exchange between systems—LANs and MANs—Specific requirements—Part 11: WLAN MAC and PHY Specifications—Amendment 5: Enhancements for Higher Throughput

IEEE Standard for Information Technology—Teleco[..] and information ...

LAN/MAN Standards Committee of the IEEE Computer Society

Static timing analysis for nanometer designs a practical approach (Rakesh Chadha, J. Bhasker (auth.)) (z-lib.org)

Static timing analysis for nanometer designs a practical approach ...

一种高性能CMOS带隙电压基准源设计朱樟明

一种高性能CMOS带隙电压基准源设计朱樟明

Virtuoso Parameterized Cell Reference

Virtuoso Parameterized Cell Reference

Inc. Cadence Design Sys tems

Frontmatter

Frontmatter

基准源、噪声、开关电容及Monte Carlo仿真

基准源、噪声、开关电容及Monte Carlo仿真

1499066564577362562-06963235

14990665645773625[..]

A low-power small-area /spl plusmn/7.28-ps-jitter 1-GHz DLL-based clock generator

A low-power small-area /spl plusmn/7.28-ps-ji[..] 1-GHz DLL-based ...

Chulwoo Kim & In-Chul Hwang & Sung-Mo Kang

Category: 射频电路-电路设计-计算机辅助设计-软件包

ADS2011射频电路设计与仿真实例

ADS2011射频电路设计与仿真实例