理工书库 lilin | Category: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing;2001;48;4;10.1109/82.933799

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Truly Nonlinear Oscillations: Harmonic Balance, Parameter Expansions, Iteration, and Averaging Methods

Truly Nonlinear Oscillations: Harmonic Balance, Parameter Expansions, ...

Ronald E. Mickens

DUTY CYCLE CORRECTION CIRCUITRY

DUTY CYCLE CORRECTION CIRCUITRY

A bandgap reference using chopping for reduction of

A bandgap reference using chopping for reduction of

半导体器件物理(第3版)-中文版-施敏-高清版

半导体器件物理(第3版)-中文版-[..]

开关电容电路从入门到精通

开关电容电路从入门到精通

PLL 设计仿真及应用

PLL 设计仿真及应用

一种高精度的CMOS带隙基准电压源

一种高精度的CMOS带隙基准电压源

Design of Sigma-Delta Converters in MATLAB® Simulink®

Design of Sigma-Delta Converters in MATLAB® Simulink®

Session 34

Session 34

Harmonic balance finite element method applications in nonlinear electromagnetics and power systems (Lu, Junwei Yamada, Sotoshi Zhao, Xiaojun) (z-lib.org)

Harmonic balance finite element method applications in nonlinear ...

A 240-nA Quiescent Current, 95.8% Efficiency AOT-Controlled Buck Converter With A<sup>2</sup>-Comparator and Sleep-Time Detector for IoT Application

A 240-nA Quiescent Current, 95.8% Efficiency AOT-Controlled ...

Wenbin Huang & Lianxi Liu & Xufeng Liao & Chengzhi Xu & Yonyuan Li

Solution-for-Design of Analog CMOS Integrated Circuits 2nd

Solution-for-Design of Analog CMOS Integrated Circuits 2nd

在线作Bode/Nyquis

在线作Bode/Nyquis

高速信令-抖动建模-分析预算

高速信令-抖动建模-分析预算

Seven Steps to Successful Analog-to-Digital Signal Conversion (Noise Calculation for Proper Signal Conditioning) (Rev. 0)

Seven Steps to Successful Analog-to-Digital Signal Conversion ...

Analog Devices, Inc.

信号与系统习题详解奥本

信号与系统习题详解奥本

Altera系列FPGA芯片IP核详解

Altera系列FPGA芯片IP核详解

IEEE Std 1801™-2018, IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems

IEEE Std 1801™-2018, IEEE Standard for Design and Verification ...

Design Automation Standards Committee of the IEEE Computer Society

Category: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing;2001;48;4;10.1109/82.933799

Nested Miller compensation in low-power CMOS design

Nested Miller compensation in low-power CMOS design

Ka Nang Leung;P.K.T. Mok