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Numerical Analysis

Numerical Analysis

Richard L. Burden

DIT-FFT至简设计实现法

DIT-FFT至简设计实现法

现代控制理论第2版 (张嗣瀛) (Z-Library)

现代控制理论第2版 (张嗣瀛) (Z-Library)

Distributed Loss-Compensation Techniques for Energy-Efficient Low-Latency On-Chip Communication

Distributed Loss-Compensation Techniques for Energy-Efficient ...

【汉化】Static Timing Analysis for Nanometer DesignsA Practical Approach

【汉化】Static Timing Analysis for Nanometer DesignsA Practical ...

CRYSTAL OSCILLATOR WITH PEAK DETECTOR AMPLITUDE CONTROL

CRYSTAL OSCILLATOR WITH PEAK DETECTOR AMPLITUDE CONTROL

低功率、高分辨率的A-D转换器@2018

低功率、高分辨率的A-D转换器@2018

音频功率放大器设计手册

音频功率放大器设计手册

（英）DouglasSelf著

A fast-settling CMOS op amp for SC circuits with 90-dB DC gain

A fast-settling CMOS op amp for SC circuits with 90-dB DC gain

K. Bult;G.J.G.M. Geelen

Modified modeling of Miller compensation for two-stage operational amplifiers

Modified modeling of Miller compensation for two-stage operational ...

H.C. Yang;D.J. Allstot

802.11 无线权威指南

802.11 无线权威指南

LAN/MAN Standards Committee of the IEEE Computer Society

低电压CMOS分数分频锁相环频率综合器关键技术研究

低电压CMOS分数分频锁相环频率综合器关键技术研究

CN101969305B-威盛电子2012-Potential conversion circuit

CN101969305B-威盛电子[..] conversion circuit

Control Systems Engineering

Control Systems Engineering

射频集成电路与系统

射频集成电路与系统

李智群王志功编著

Session 8: Ultra-High-Speed Wireline

Session 8: Ultra-High-Speed Wireline

IEEE Std 802.11b-1999

IEEE Std 802.11b-1999

A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with over 80-dB SFDR - Solid-State Circuits, IEEE Journal of

A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with ...

Category: IEEE Microwave Magazine;2019;20;5;10.1109/MMM.2019.2898022

Smoothing the Way for Digital Phase-Locked Loops: Clock Generation in the Future with Digital Signal Processing for Mitigating Spur and Interference

Smoothing the Way for Digital Phase-Locked Loops: Clock Generation ...

Cheng-Ru Ho & Mike Shuo-Wei Chen