0-306-47052-7_Boo[..]
未知
1.5Bit 级pipelined+ADC典型单[..]
Xilinx PG153 LogiCORE IP AXI Quad Serial Peripheral Interface ...
Xilinx, Inc.
Smoothing the Way for Digital Phase-Locked Loops: Clock Generation ...
Cheng-Ru Ho & Mike Shuo-Wei Chen
基于功耗优化的Pipelined+[..] (1)
asicon.2009.53514[..] Power Supply Rejection
一种LDO使能控制端失效的分析方法
Low-noise monolithic amplifier design: Bipolar versus CMOS
Memory systems_ cache, DRAM, disk -- Bruce Jacob, Spencer Ng, ...
Microsoft Word - 131_63212-IJAER ok 4118-modified document
AA
集成电路设计中的电源管理技术
Founder Electronics Ltd
哈尔滨工业大学硕士毕业论文模板
yinhf
电源芯片中CMOS带隙基准源与微调[..] (1)
HFSS电磁仿真设计从入门到精通
Wiener-Khinchin theorem
高效率峰值电流模BOOST型DC-[..]
jlxu
introduction.ppt
kdjwang
Session 29V
FinFET Devices for VLSI Circuits and Systems
Samar K. Saha