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模拟集成电路信号完整性中抖动与振铃问题的研究

模拟集成电路信号完整性中抖动与振铃[..]

Analysis and Design of Transimpedance Amplifiers for Optical Receivers

Analysis and Design of Transimpedance Amplifiers for Optical ...

Constraining Designs for Synthesis and Timing Analysis A Practical Guide to Synopsys Design Constraints (SDC) (Sridhar Gangadharan, Sanjay Churiwala (auth.)) (z-lib.org)

Constraining Designs for Synthesis and Timing Analysis A Practical ...

Microsoft Word - 0TitlePageVbook.doc

Microsoft Word - 0TitlePageVbook.doc

[集成电路掩膜板设计].IC.Mask.Design

[集成电路掩膜板设计].IC.Ma[..]

Fundamentals of Digital Logic with Verilog Design, THIRD EDITION

Fundamentals of Digital Logic with Verilog Design, THIRD EDITION

Stephen Brown & Zvonko Vranesic

The Method of Moments in Electromagnetics, Second Edition

The Method of Moments in Electromagnetics, Second Edition

Gibson, Walton C.

A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with over 80-dB SFDR - Solid-State Circuits, IEEE Journal of

A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with ...

A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process

A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process

Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Yin-Zu Lin

Cadence高速电路板设计

Cadence高速电路板设计

PDFￗﾪﾻﾻￆ￷

PDFￗﾪﾻﾻￆ￷

PDFￗﾪﾻﾻￆ￷

Session 20

Session 20

Sampled Systems and the Effects of Clock Phase Noise and Jitter Application Note (AN-756)

Sampled Systems and the Effects of Clock Phase Noise and Jitter ...

Analog Devices, Inc.

Session 1: Plenary Session — Invited Papers

Session 1: Plenary Session — Invited Papers

Session 13: Cyro-CMOS for Quantum Computing

Session 13: Cyro-CMOS for Quantum Computing

射频电路与芯片设计要点（中文版）

射频电路与芯片设计要点（中文版）

高速高精度ADC中基准电压源的研究与设计 (1)

高速高精度ADC中基准电压源的研究与设计 (1)

te.2005.杨氏零点再发现

te.2005.杨氏零点再发现

Category: 芋头网出品

Analog IC Design with Low-Dropout Regulators, Second Edition

Analog IC Design with Low-Dropout Regulators, Second Edition

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