理工书库 lilin | Category: with a maximum throughput of at least 100 Mb/s

Discover (Random Books)

微处理器设计：从设计规划到工艺制造

微处理器设计：从设计规划到工艺制造

Session 36

Session 36

Verilog HDL Design Examples

Verilog HDL Design Examples

Joseph Cavanagh

ESD in Silicon Integrated Circuits

ESD in Silicon Integrated Circuits

信号与系统（奥本海姆）

信号与系统（奥本海姆）

Smoothing the Way for Digital Phase-Locked Loops: Clock Generation in the Future with Digital Signal Processing for Mitigating Spur and Interference

Smoothing the Way for Digital Phase-Locked Loops: Clock Generation ...

Cheng-Ru Ho & Mike Shuo-Wei Chen

模拟CMOS集成电路第二版拉扎维 (拉扎维)

模拟CMOS集成电路第二版拉扎维 (拉扎维)

使用电压基准进行设计的提示和技巧

使用电压基准进行设计的提示和技巧

Texas Instruments, Incorporated [ZHCC347,*]

Topics in Multiple-Loop Regulators and Current-Mode Programming

Topics in Multiple-Loop Regulators and Current-Mode Programming

verilog HDL那些事

verilog HDL那些事

Fundamental Principles Behind the Sigma-Delta ADC Topology Part 1

Fundamental Principles Behind the Sigma-Delta ADC Topology Part ...

Michael Clifford & Analog Devices Inc

SARADC设计

SARADC设计

Spectre Circuit Simulator Reference

Spectre Circuit Simulator Reference

Inc. Cadence Design Sys tems

CN104601160B-灿芯半导体2017-带ESD的高速输出级

CN104601160B-灿芯半导[..]

Triple-Speed Ethernet Intel® FPGA IP User Guide

Triple-Speed Ethernet Intel® FPGA IP User Guide

Intel Corporation

射频集成电路

射频集成电路

带隙基准电路的研究

带隙基准电路的研究

模拟电路版图的艺术

模拟电路版图的艺术

Category: with a maximum throughput of at least 100 Mb/s

IEEE Standard for Information Technology—Telecommunications and information exchange between systems—LANs and MANs—Specific requirements—Part 11: WLAN MAC and PHY Specifications—Amendment 5: Enhancements for Higher Throughput

IEEE Standard for Information Technology—Teleco[..] and information ...

LAN/MAN Standards Committee of the IEEE Computer Society