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CN201887731U-可修调的高精度RC 振荡电路

CN201887731U-可修调的[..] 振荡电路

A TIA in CMOS 0.18um

A TIA in CMOS 0.18um

Quantus Techgen Reference Manual

Quantus Techgen Reference Manual

Phase Locked Loops for Wireless Communications

Phase Locked Loops for Wireless Communications

Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design by Mourad Fakhfakh, Esteban Tlelo-Cuautle, Patrick Siarry (eds.) (z-lib.org)

Computational Intelligence in Analog and Mixed-Signal (AMS) ...

Altera系列FPGA芯片IP核详解

Altera系列FPGA芯片IP核详解

ISSCC2021-T4-Measuring and Evaluating the Security Level of Circuits

ISSCC2021-T4-Meas[..] and Evaluating the Security Level of ...

Advanced_Signal_Integrity_for_High-Speed_Digital_Designs

Advanced_Signal_I[..]

CMOS Sigma-Delta Converters Practical Design Guide

CMOS Sigma-Delta Converters Practical Design Guide

Verilog HDL Design Examples

Verilog HDL Design Examples

Joseph Cavanagh

AMBA 4 AXI4-Stream Protocol Specification

AMBA 4 AXI4-Stream Protocol Specification

Keliu Shu-2005 CMOS PLL Synthesizers Analysis and Design

Keliu Shu-2005 CMOS PLL Synthesizers Analysis and Design

用于OFDM+UWB系统中的中频滤波器和可变增益放大器的研究设计

用于OFDM+UWB系统中的中频滤[..]

CMOS模拟集成电路设计与仿真实例——基于Cadence ADE

CMOS模拟集成电路设计与仿真实例[..] ADE

SystemVerilog验证测试平台编写指南

SystemVerilog验证测试平台编写指南

低中频接收机中复数滤波器的设计

低中频接收机中复数滤波器的设计

A low-power small-area /spl plusmn/7.28-ps-jitter 1-GHz DLL-based clock generator

A low-power small-area /spl plusmn/7.28-ps-ji[..] 1-GHz DLL-based ...

Chulwoo Kim & In-Chul Hwang & Sung-Mo Kang

逐达逼近型模数转换器的低功耗与高速设计技术研究

逐达逼近型模数转换器的低功耗与高速[..]

Category: multiple output

IEEE Standard for Information Technology—Telecommunications and information exchange between systems—LANs and MANs—Specific requirements—Part 11: WLAN MAC and PHY Specifications—Amendment 5: Enhancements for Higher Throughput

IEEE Standard for Information Technology—Teleco[..] and information ...

LAN/MAN Standards Committee of the IEEE Computer Society