A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
Session 5
未知
Session 3: Highlighted Chip Releases: Modern Digital SoCs
2016 Book Transformer-Based[..]
bstj.1932.Nyquist, H.-Regeneration Theory
高性能小数分频频率合成技术 刘祖深 压缩版
COMS集成锁相环电路设计
LDO工作原理详解
数字图像处理
（美）冈萨雷斯，（美）伍兹著
EESM692
Prof. Alex Leung
CN105824349A-上海巨微[..] bandgap
Harmonic balance finite element method applications in nonlinear ...
AMPLIFIER ARCHITECTURE AND APPLICATION THEREOF TO A BAND-GAP ...
AMBA 3 APB Protocol Specification
ARM Limited
Introduction to AMBA Bus System
吳欣龍
TheDesigner’sGuid[..]
esd-circuits-and-[..]
高精度带隙基准电压源研究与设计
田兴果
AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...
Xilinx, Inc.
AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)
JESD204 v7.2 LogiCORE IP Product Guide (PG066)
Xilinx PG153 LogiCORE IP AXI Quad Serial Peripheral Interface ...
Xilinx DS558, LogiCORE IP DDS Compiler v4.0, Data Sheet
Xilinx DS534, FIR Compiler v5.0, Data Sheet