Session 17
未知
射频设计中的层次化建模
Session 11: Advanced Wireline Links and Techniques
Design of Ultra Wideband Power Transfer Networks
Binboga Siddik Yarman
一种自参考结构的高速高精度片上时钟[..]
Microsoft Word - RFKitDoc_v1 3.doc
alanw
基于Latch的CMOS动态比较器的研究
MIPI Alliance Specification for I3C Basic, Version 1.0
MIPI Alliance & Inc.
动态系统的反馈控制
（美）吉恩 F.富兰克林（Gene F.Franklin），（美）J.大卫·鲍威尔（J.D[..] Powell），（美）阿巴斯·埃马米·纳尼（Abbas ...
Digital Phase Lock Loops Architectures and Applications (Professor ...
4<8=8AB@0B>@
数字滤波器的MATLAB与FPGA[..]
High Efficiency RF and Microwave Solid State Power Amplifiers
Paolo Colantonio, Franco Giannini & Ernesto Limiti
概率论基础教程 原书第9版
（美）罗斯著
数字信号处理 理论、算法与实现(第三版) 清华大学出版社，2012 (胡广书) (Z-Library)
Session 18
Session 28V
A 76 dB 1.7 GHz 0.18 m CMOS Tunable TIA Using Broadband Current ...
Hossein Miri Lavasani & Wanling Pan & Brandon Harrington & Reza Abdolvand & Farrokh Ayazi
Electromagnetics (John D. Kraus, Keith R. Carver) (Z-Library)
AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...
Xilinx, Inc.
AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)
Xilinx PG153 LogiCORE IP AXI Quad Serial Peripheral Interface ...
Xilinx DS558, LogiCORE IP DDS Compiler v4.0, Data Sheet
Xilinx DS534, FIR Compiler v5.0, Data Sheet