JSSC 202212
未知
Assura Physical Verifica tion User Guide
Inc. Cadence Design Sys tems
Design Optimization of Power and Area of Two-Stage CMOS Operational ...
Telugu Maddileti;Govindarajulu Salendra;Chandra Mohan Reddy ...
信号分析与处理_MATLAB语言及应用
http://www.pris.edu.cn
CN201887731U-可修调的[..] 振荡电路
线性代数及其应用（第5版－Gilbert Strang
Microsoft PowerPoint - 第十一章 带隙基准 [兼容模式]
模拟集成电路的分析与设计格雷 第四版
OPAMP设计-tangzhangwen
Zhangwen Tang
《自动控制原理》[卢京潮 编著]
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
Middlebrook Part 2
mwidmer
模拟CMOS集成电路设计 第2版14609998
IEEE Standard for Ethernet
Session 21
Spectre Circuit Simulator Components and Device Models Reference
高速低功耗SAR ADC的关键技术研究与系统设计
HKF
Session 25: DRAM
Xilinx DS249 LogiCORE IP CORDIC v4.0, Data Sheet,
Xilinx, Inc.