A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Ying-Zu Lin & Chung-Ming Huang & Chih-Hao Huang & Linkai Bu & Chih-Chung Tsai
CMOS 集成电路设计手册 第3版·模拟电路篇=CMOS CIRCUIT DESIGN LAYOUT AND SIMULATION ...
未知
深入理解linux虚拟内存管理（英文）
Analog Behavioral Modeling with the Verilog-A Language
2004Beek
数字信号处理 时域离散随机信号处理
阔永红
反馈系统
Feedback Systems An Introduction for Scientists & Engineers (2008, Princeton University Press)
Microelectronic circuits 6th edition
基于功耗优化的Pipelined+[..] (1)
ISSCC2021-T1-Fund[..] of RF and Mm-Wave Power Amplifier Designs
RISC-V IOMMU Architecture Specification
IOMMU Task Group
5.0Gbps高速串行USB3.0[..]
Microstrip Filters for RFMicrowave Applications, Second Edition ...
4<8=8AB@0B>@
ISSCC2021-SC1-Int[..] to PLLs Phase Noise, Modeling, and Key ...
ISSC2021 SESSION 2
高效率 PWM 控制电流型 DC-DC
Lenovo User
AN 812: Platform Designer System Design Tutorial
Intel Corporation
93.张强-高性能Rail to Rail恒定跨导CMOS运算放大器
IEEE Standard for Ethernet