A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ...
Chun-Cheng Liu;Soon-Jyh Chang;Guan-Ying Huang;Ying-Zu Lin
THE DESIGN OF MASTER-SLAVE DLL FOR DDR2 SDRAM CONTROLLER IN ...
iccad095
Embedded Design Handbook
Intel Corporation
Analysis and Design of Monolithic, High PSR, Linear Regulators ...
Vishal
模拟集成电路设计与仿真 何乐年
Edward
JSSC 202212
未知
一种高精密CMOS带隙基准源 王彦
ISSC2021 SESSION 2
2010_FrontMatter_[..]
Steve Bonney
Modified modeling of Miller compensation for two-stage operational ...
H.C. Yang;D.J. Allstot
基于延迟锁相环的时钟发生器设计
基于FPGA的嵌入式图像处理系统设计 原魁[译]
Digital Logic and Computer Design
M. MORRIS MANO
Generate ESD Source in ADS
TU,NASH (K-Taiwan,ex1)
Universal Verification Methodology (UVM) Cookbook
Functional Verification Methodology Team - Mentor & A Siemens Business
Analysis and Design of Analog Integrated Circuits, 5th Edition
Paul R. Gray
CMOS模拟集成电路设计
（美）艾伦，（美）霍尔伯格著
Microsoft PowerPoint - Random_Offset_CMO[..]
Mama
Avalon Verification IP Suite User Guide
Altera Corporation
Avalon® Interface Specifications