理工书库 lilin | Category: This core implements a JESD204B interface supporting a line rate of up to 12.5 Gb/s on 1- 12 lanes using GTX or GTH transceivers in Zynq-7000 AP SoC devices

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ISSCC2021 Session 28

ISSCC2021 Session 28

Fast analytical techniques for electrical and electronic circuits

Fast analytical techniques for electrical and electronic circuits

Vatche Vorperian

ISSCC2021-T5-Calibration Techniques in ADCs

ISSCC2021-T5-Cali[..] Techniques in ADCs

2-Stage OTA Design

2-Stage OTA Design

TI-CICC2006-A Sub-i V Low-Noise Bandgap Voltage Reference

TI-CICC2006-A Sub-i V Low-Noise Bandgap Voltage Reference

模拟集成电路的分析与设计格雷第四版

模拟集成电路的分析与设计格雷第四版

模拟集成电路

模拟集成电路

LDO线性稳压器中高性能误差放大器的设计

LDO线性稳压器中高性能误差放大器的设计

Analog Circuit Design Volume 2 Immersion in the Black Art of Analog Design.

Analog Circuit Design Volume 2 Immersion in the Black Art of ...

Bob Dobkin,John Hamburger

Session 36

Session 36

Design of Analog CMOS Integrated Circuits, Second Edition

Design of Analog CMOS Integrated Circuits, Second Edition

开关电源设计第3版

开关电源设计第3版

（美）普利斯曼，比利斯，莫瑞著

线性代数及其应用（第5版－Gilbert Strang

线性代数及其应用（第5版－Gilbert Strang

DjVu Document

DjVu Document

CN104601160B-灿芯半导体2017-带ESD的高速输出级

CN104601160B-灿芯半导[..]

Session 4

Session 4

RF CMOS Oscillators for Modern Wireless Applications

RF CMOS Oscillators for Modern Wireless Applications

Masoud Babaie, Mina Shahmohammadi & Robert Bogdan Staszewski

Virtuoso Multi-Mode Simulation with Spectre Platform

Virtuoso Multi-Mode Simulation with Spectre Platform

Category: This core implements a JESD204B interface supporting a line rate of up to 12.5 Gb/s on 1- 12 lanes using GTX or GTH transceivers in Zynq-7000 AP SoC devices

JESD204 v7.2 LogiCORE IP Product Guide (PG066)

JESD204 v7.2 LogiCORE IP Product Guide (PG066)