理工书库 lilin | Category: This core implements a JESD204B interface supporting a line rate of up to 12.5 Gb/s on 1- 12 lanes using GTX or GTH transceivers in Zynq-7000 AP SoC devices

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Handbook of Power Management Circuits

Handbook of Power Management Circuits

Session 5

Session 5

模拟集成电路分析与设计（第二版）

模拟集成电路分析与设计（第二版）

Front Cover Circuit Analysis I.qxd (Page 1)

Front Cover Circuit Analysis I.qxd (Page 1)

Karris, Steven T.

高速高精度ADC中基准电压源的研究与设计 (1)

高速高精度ADC中基准电压源的研究与设计 (1)

简并点优化的高性能带隙基准电路应建华

简并点优化的高性能带隙基准电路应建华

Session 22

Session 22

High Speed Data Converters

High Speed Data Converters

射频电路设计：理论与应用 ([美]Reinhold Ludwig) (Z-Library)

射频电路设计：理论与应用 ([美]Reinhold Ludwig) (Z-Library)

一种具有温度补偿高电源抑制比的带隙基准源何捷 (1)

一种具有温度补偿高电源抑制比的带隙基准源何捷 (1)

Aperture Uncertainty and ADC System Performance Application Note (AN-501)

Aperture Uncertainty and ADC System Performance Application ...

Analog Devices, Inc.

设计模式：可复用面向对象软件的基础

设计模式：可复用面向对象软件的基础

Herbst-MIT2011--A Low-Noise Bandgap Voltage Reference Employing Dynamic Element Matching

Herbst-MIT2011--A Low-Noise Bandgap Voltage Reference Employing ...

ISSCC2021-SC3-Clocking, Clock Distribution, and Clock Management in WirelineWireless Subsystems

ISSCC2021-SC3-Clo[..] Clock Distribution, and Clock Management ...

New developments in IC voltage regulators

New developments in IC voltage regulators

Practical RF Circuit Design for Modern Wireless Systems_ Passive Circuits and Systems Volume I

Practical RF Circuit Design for Modern Wireless Systems_ Passive ...

Session 13: Cyro-CMOS for Quantum Computing

Session 13: Cyro-CMOS for Quantum Computing

Wishbone B4

Wishbone B4

Category: This core implements a JESD204B interface supporting a line rate of up to 12.5 Gb/s on 1- 12 lanes using GTX or GTH transceivers in Zynq-7000 AP SoC devices

JESD204 v7.2 LogiCORE IP Product Guide (PG066)

JESD204 v7.2 LogiCORE IP Product Guide (PG066)