理工书库 lilin | Category: This core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.

Discover (Random Books)

Optimum Feedback Amplifier Design For Control Systems

Optimum Feedback Amplifier Design For Control Systems

Timothy E. Biesecker

CMOS模拟集成电路

CMOS模拟集成电路

Session 5: Analog Interfaces

Session 5: Analog Interfaces

ISSCC2021-T3-Silicon Photonics – from Basics to ASICs

ISSCC2021-T3-Silicon Photonics – from Basics to ASICs

CMOS 带隙基准源研究-tangzhangwen

CMOS 带隙基准源研究-tangzhangwen

jssc.2005.Replica Compensated Linear Regulators for PLLs

jssc.2005.Replica Compensated Linear Regulators for PLLs

Temperature in EMX

Temperature in EMX

基准电压源和线性稳压器的设计-tangzhangwen

基准电压源和线性稳压器的设计-ta[..]

A 25Gb/s PAM4 Transmitter in 90nm CMOS SOI

A 25Gb/s PAM4 Transmitter in 90nm CMOS SOI

相位噪声jitter基本定义

相位噪声jitter基本定义

ISSCC2021 Session 27

ISSCC2021 Session 27

CN102393785B-砂力杰-BG失调消除

CN102393785B-砂力杰-[..]

Simulating Switched-Capacitor Filters with SpectreRF

Simulating Switched-Capacitor Filters with SpectreRF

Constraining Designs for Synthesis and Timing Analysis A Practical Guide to Synopsys Design Constraints (SDC) (Sridhar Gangadharan, Sanjay Churiwala (auth.)) (z-lib.org)

Constraining Designs for Synthesis and Timing Analysis A Practical ...

A gm/ID Based Methodology for the Design of CMOS Analog Circuits andd Its Application to the S - Solid-State Circuits, IEEE Journal of

A gm/ID Based Methodology for the Design of CMOS Analog Circuits ...

FinFET Modeling for IC Simulation and Design

FinFET Modeling for IC Simulation and Design

Session 32

Session 32

模拟电路与数字电路

模拟电路与数字电路

Category: This core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.

AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)

AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)