高速数字电路设计中信号完整性分析与研究
未知
模拟IC设计
拉扎维
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Ying-Zu Lin & Chung-Ming Huang & Chih-Hao Huang & Linkai Bu & Chih-Chung Tsai
Michiel Steyaert CMOS CELLULAR RECEIVER FRONT-ENDS
Cadence Physical Verifi cation User Guide
Inc. Cadence Design Sys tems
一种应用于DC DC转换器的自举电路设计
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...
D.J. Foley;M.P. Flynn
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
自适应滤波器原理
（美）赫金 & 郑宝玉等译
Synthesis of Arithmetic Circuits : FPGA, ASIC, and Embedded ...
Deschamps & Jean-Pierre. & Bioul & Gery Jean Antoine. & Sutter & Gustavo D.
微波工程（第四版） (David M.Pozar) (Z-Library)
PowerManagmentIC
khchen
Sahrling M. Analog Circuit Simulators for Integrated Circuit ...
Low-Jitter Process-Independent DLL and PLL Based on Self-Biased ...
IEEE
X-Parameters
DAVID E. ROOT
深入Linux内核架构
Frequency Compensation of Op-amp and its types Circuit Digest
Fire and Ice QXC to Quantus Migration Guide
Embedded Peripherals IP User Guide
Intel Corporation