CMOS-Voltage-Refe[..]
4<8=8AB@0B>@
A Low Power Two Stages CMOS OpAmp
未知
Session 26V
CN104601160B-灿芯半导[..]
基于 DLL倍频技术的 1GHz本地振荡器设计 英文 李金城
ISF_TUTORIAL
YIZHE HU
Low-noise monolithic amplifier design: Bipolar versus CMOS
Sampled Systems and the Effects of Clock Phase Noise and Jitter ...
Analog Devices, Inc.
模拟CMOS集成电路设计 答案(拉扎维)
2016 Book Transformer-Based[..]
bstj.1932.Nyquist, H.-Regeneration Theory
Michiel Steyaert CMOS CELLULAR RECEIVER FRONT-ENDS
bingdian001.com
数字集成电路物理设计
陈春章 艾 霞 王国雄 编著
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
Session 12
Session 30: Non-Volatile Memories
集成电路静态时序分析与建模
刘峰编著
Vivado Design Suite User Guide: Logic Simulation (UG900)
Xilinx, Inc.