CN106656160A-上海集成[..]
未知
Tempus User Guide
Inc. Cadence Design Sys tems
Stability for Op Amps
低电压CMOS分数分频锁相环频率综合器 关键技术研究
LU HUNG
一种应用于LDO的可编程电流限电路设计
A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm ...
Kuan-Yueh Shen & Syed Feruz Syed Farooq & Yongping Fan & Khoa Minh Nguyen & Qi Wang & Mark L. Neidengard & Nasser Kurd & Amr Elshazly
TI-CICC2006-A Sub-i V Low-Noise Bandgap Voltage Reference
CMOS Sigma-Delta Converters Practical Design Guide
4<8=8AB@0B>@
射频设计中的层次化建模
计算电磁场的矩量法（PDF）
全数字锁相环建模及分析代码-2014
Phase Locked Loops for Wireless Communications
用于低相位噪声LC VCO的低噪声可调LDO的设计
TI-运算放大器
Frontmatter
Standard Verification Rule Format (SVRF) Manual 2023
Siemens Industry Software
低压高速LDO电路系统的分析与设计
Session 30: Non-Volatile Memories
Design Procedure for Two-Stage CMOS Opamp using gm/ID design ...
Bakr Hesham & El-Sayed Hasaneen & Hesham F. A. Hamed