Smoothing the Way for Digital Phase-Locked Loops: Clock Generation ...
Cheng-Ru Ho & Mike Shuo-Wei Chen
现代控制系统
未知
信号与系统 2nd 西蒙赫金
finite elemennt anlysis in ansys
kubik
一种快速瞬态响应的无片外电容LDO
通信标准对数据转换器的要求V1.0
高效率boost DCDC电源管理芯片设计技术研究
wumin
Session 16
基于斩波技术的CMOS运算放大器失[..]
一种快速瞬态响应LDO的设计与实现
TOM
eetop.cn (Paper)The Flipped Voltage Follower A Useful Cell for
RC OSCILLATOR WITH ADDITIONAL NVERTER IN SERIES WITH CAPACTOR
Electronic Circuit and System Simulation Methods
Lawrence T. Pillage, Ronald A. Rohrer, Chandramouli Visweswariah
A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Yin-Zu Lin
学校代码 10530 学 号 201110061316
zxsr70885
Phase Locked Loops for Wireless Communications
Practical RF Amplifier Design and Performance Optimization with ...
Session 30: Non-Volatile Memories
IEEE Standard for Ethernet