理工书库 lilin | Category: IEEE Journal of Solid-State Circuits;2010;45;4;10.1109/JSSC.2010.2042254

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微带电路——清华

微带电路——清华

Layout Techniques for Integrated Circuit Designers

Layout Techniques for Integrated Circuit Designers

CN104977963A-兆易创新-一种无运放低功耗高电源抑制比的带隙基准 (1)

CN104977963A-兆易创新[..] (1)

$Enhanced phase noise modeling of fractional-N frequency synthesizers$

Enhanced phase noise modeling of fractional-N frequency synthesizers

H. Arora;N. Klemmer;J.C. Morizio;P.D. Wolf

Microsoft PowerPoint - 第十一章带隙基准 [兼容模式]

Microsoft PowerPoint - 第十一章带隙基准 [兼容模式]

模拟集成电路信号完整性中抖动与振铃问题的研究

模拟集成电路信号完整性中抖动与振铃[..]

PlanarSpiralInductors,PlanarAntennasandEmbeddedPlanarTransformers

PlanarSpiralInduc[..]

Numerical Analysis (Richard L. Burden, J. Douglas Faires etc.) (z-lib.org) (1)

Numerical Analysis (Richard L. Burden, J. Douglas Faires etc.) ...

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop ...

Yongsun Lee & Taeho Seong & Seyeon Yoo & Jaehyouk Choi

Next-Generation ADCs, High-Performance Power Management, and Technology Consider

Next-Generation ADCs, High-Performance Power Management, and ...

Modified modeling of Miller compensation for two-stage operational amplifiers

Modified modeling of Miller compensation for two-stage operational ...

H.C. Yang;D.J. Allstot

High-Speed Architecture for a Programmable Frequency Divider and a Dual-Modulus Prescaler - Solid-State Circuits, IEEE Journal of

High-Speed Architecture for a Programmable Frequency Divider ...

ISSCC2021-SC2-PLL Architectures, Tradeoffs, and Key Application Considerations

ISSCC2021-SC2-PLL Architectures, Tradeoffs, and Key Application ...

BesserWM35.vp:CorelVentura 7.0

BesserWM35.vp:Cor[..] 7.0

一种应用于MCU待机模式的超低功耗LDO设计

一种应用于MCU待机模式的超低功耗[..]

Michiel Steyaert CMOS CELLULAR RECEIVER FRONT-ENDS

Michiel Steyaert CMOS CELLULAR RECEIVER FRONT-ENDS

ADI 技术指南合集

ADI 技术指南合集

NumericalOptimization

NumericalOptimiza[..]

Category: IEEE Journal of Solid-State Circuits;2010;45;4;10.1109/JSSC.2010.2042254

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ...

Chun-Cheng Liu;Soon-Jyh Chang;Guan-Ying Huang;Ying-Zu Lin