理工书库 lilin | Category: some will apply specifically to our case in question.

Discover (Random Books)

反馈运算放大器电路的噪声分析和设计

反馈运算放大器电路的噪声分析和设计

学校代码 10530 学号 201110061316

学校代码 10530 学号 201110061316

Abidi-Pan, Hui.University of California, Los Angeles

Abidi-Pan, Hui.University of California, Los Angeles

A TIA in CMOS 0.18um

A TIA in CMOS 0.18um

信号与系统（奥本海姆）

信号与系统（奥本海姆）

Physical design essentials an ASIC design implementation perspective (Khosrow Golshan) (z-lib.org)

Physical design essentials an ASIC design implementation perspective ...

A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process

A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process

Wenzha Yang & Yi Zhang & Enwen Dai & ZhiLin Feng & Wei Li

看一个TI老工程师如何驯服精密放大器

看一个TI老工程师如何驯服精密放大器

离散数学及其应用

离散数学及其应用

一种低压CMOSLDO稳压电源电路

一种低压CMOSLDO稳压电源电路

模拟CMOS集成电路设计第2版14609998

模拟CMOS集成电路设计第2版14609998

CMOS射频集成电路分析与设计 (池保勇, 余志平, 石秉学) (z-lib.org)

CMOS射频集成电路分析与设计 (池保勇, 余志平, 石秉学) (z-lib.org)

A gm/ID Based Methodology for the Design of CMOS Analog Circuits andd Its Application to the S - Solid-State Circuits, IEEE Journal of

A gm/ID Based Methodology for the Design of CMOS Analog Circuits ...

Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques [Paper] - Solid-State Circuits, IEEE Journal of

Low-Jitter Process-Independent DLL and PLL Based on Self-Biased ...

High Efficiency RF and Microwave Solid State Power Amplifiers

High Efficiency RF and Microwave Solid State Power Amplifiers

Paolo Colantonio, Franco Giannini & Ernesto Limiti

TWO-STAGE FULLY-DIFFERENTIAL OPAMPS

TWO-STAGE FULLY-DIFFERENTIAL OPAMPS

DESIGN WITH OPERATIONAL AMPLIFIERS AND

DESIGN WITH OPERATIONAL AMPLIFIERS AND

一种极低静态电流LDO线性稳压器的设计

一种极低静态电流LDO线性稳压器的设计

Category: some will apply specifically to our case in question.

Understanding Jitter Requirements of PLL-Based Processors Application Note (EE-261)

Understanding Jitter Requirements of PLL-Based Processors Application ...

ANALOG DEVICES INC.