A 76 dB 1.7 GHz 0.18 m CMOS Tunable TIA Using Broadband Current ...
Hossein Miri Lavasani & Wanling Pan & Brandon Harrington & Reza Abdolvand & Farrokh Ayazi
BOOK-010005000009[..]
zhenying.luo
Session 20
未知
Artificial Intelligence: A Modern Approach, Global Edition, ...
Stuart Russell / Peter Norvig
compact trimming design of a high precision reference
全单片集成的多模CMOS正交频率综[..]
SSReader Print.
Dean
Low-noise monolithic amplifier design: Bipolar versus CMOS
Research and Design of Buck-Boost DC-DC Converter
CNKI
HarmonicBalance
Operational Amplifiers Theory and Design (Johan Huijsing (auth.)) ...
芯片I／O缓冲及ESD电路设计
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
一种自适应补偿的宽输入LDO设计
14612565
Physical design essentials an ASIC design implementation perspective ...
开关电源设计 第3版
（美）普利斯曼，比利斯，莫瑞著
最优化计算方法 (刘浩洋, 户将, 李勇锋，文再文) (Z-Library) (1)
IEEE Standard for Ethernet