Design Procedure for Two-Stage CMOS Transconductance Operational ...
未知
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...
D.J. Foley;M.P. Flynn
CN106357266B-华为20[..]
锁相环型频率综合器中的高速分频器 袁泉
CMOS模拟集成电路设计与仿真实例[..] ADE 陈成颖
Digital Beamforming-Based Massive MIMO Transceiver for 5G Millimeter-Wave ...
Binqi Yang & Zhiqiang Yu & Ji Lan & Ruoqiao Zhang & Jianyi Zhou & Wei Hong
Session 11: Advanced Wireline Links and Techniques
数值计算方法 (2)
现代控制理论基础 第4版 (孙炳达) (Z-Library)
作者
射频电路基础 (赵建勋,邓军) (Z-Library)
A 2.7-V 900-MHz CMOS LNA and Mixer - Solid-State Circuits, IEEE ...
IEEE
Universal Serial Bus 3.0 Specification
<C8ABD2B3D5D5C6AC>
Administrator
Computer Graphics, C Version (2nd Ed.)
Donald Hearn, M. Pauline Baker
基于XILINX FPGA的OFDM通信系统基带设计
Session 31: Analog Techniques
Sampled Systems and the Effects of Clock Phase Noise and Jitter ...
Analog Devices, Inc.
Electric Machines; Transients, Control Principles, Finite Element ...
Ion Boldea & Lucian N. Tutelea
IEEE Std 1801™-2018, IEEE Standard for Design and Verification ...
Design Automation Standards Committee of the IEEE Computer Society