Cadence PVS Developers Guide
Inc. Cadence Design Sys tems
A 2-dB noise figure 900-MHz differential CMOS LNA - Solid-State ...
未知
Advanced_Signal_I[..]
【汉化】Static Timing Analysis for Nanometer DesignsA Practical ...
Tempus User Guide
Triple-Speed Ethernet Intel® FPGA IP User Guide
Intel Corporation
ESD设计与综合
作者
PlanarSpiralInduc[..]
RF Circuit Design (Information and Communication Technology ...
Richard C. Li
LDO模拟集成电路设计
Fundamentals of Digital Logic with Verilog Design, THIRD EDITION
Stephen Brown & Zvonko Vranesic
一种具有采样保持功能的开关电容积分器 宋文清
CNKI
Design Procedure for Two-Stage CMOS Transconductance Operational ...
模拟CMOS集成电路 第二版 拉扎维 (拉扎维)
WLAN射频接收机集成电路设计与研究
JESD204 v7.2 LogiCORE IP Product Guide (PG066)
Xilinx, Inc.
Understanding Jitter Requirements of PLL-Based Processors Application ...
ANALOG DEVICES INC.
模拟CMOS集成电路设计（拉扎维）答案
陈鹏远
SystemVerilog 验证方法学 - Verification Methodology Manual for SystemVerilog
Janick Bergeron & Eduard Cemy & Alan Hunter & Andrew Nightingale 著 & 夏宇闻 译