OPAMP设计-tangzhangwen
Zhangwen Tang
Topic 8 Circuit Envelope
Rashaunda Henderson
AN 812: Platform Designer System Design Tutorial
Intel Corporation
Jespers-The gm ID Methodology, a sizing tool
未知
Session 30
Static timing analysis for nanometer designs a practical approach ...
0132642786.pdf
Neil H. E. Weste
Analysis and design of monolithic, high PSR, linear regulators ...
综合与Design Compiler
阳晔
Session 22
Precise delay generation using coupled oscillators
J.G. Maneatis & M.A. Horowitz
Continuous-Time Sigma-Delta AD Conversion Fundamentals, Performance ...
Digital Logic and Computer Design
M. MORRIS MANO
Dynamic offset compensated CMOS amplifiers-Huijsing
0-306-47052-7_Boo[..]
Dynamic Response of Linear Systems Impact of Pole & Zero Locations
PHASE ERROR CANCELLATION
CMOS带隙基准源研究与设计
dwd
Xilinx DS534, FIR Compiler v5.0, Data Sheet
Xilinx, Inc.
Xilinx DS558, LogiCORE IP DDS Compiler v4.0, Data Sheet
Xilinx PG153 LogiCORE IP AXI Quad Serial Peripheral Interface ...
JESD204 v7.2 LogiCORE IP Product Guide (PG066)
AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)
AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...