Cadence SKILL Lan guage Reference
Inc. Cadence Design Sys tems
Power Management Techniques for Integrated Circuit Design
Ke-Horng Chen
CMOS射频集成电路分析与设计 (池保勇, 余志平, 石秉学) (z-lib.org)
未知
A 76 dB 1.7 GHz 0.18 m CMOS Tunable TIA Using Broadband Current ...
Hossein Miri Lavasani & Wanling Pan & Brandon Harrington & Reza Abdolvand & Farrokh Ayazi
ISSCC2021-T5-Cali[..] Techniques in ADCs
FPGA数字信号处理设计教程：Sy[..] Generator入门与提高 11938681
Calibre® DESIGNrev Layout Viewer User's Manual
Siemens Industry Software
Robust Design of LV/LP Low-Distortion CMOS Rail-to-Rail Input ...
一种快速瞬态响应LDO的设计与实现
TOM
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
DDR3存储器接口电路的设计与实现[..]
教材：李庆扬数值分析-第五版
ISSCC2020-01 Visuals
Steve Bonney
Single miller capacitor frequency compensation technique for ...
Session 35
一种应用于LDO的可编程电流限电路设计
AMBA总线规范_V2.0
kongsuo
Analog Circuit Design Volume 3 Design Note Collection
Bob Dobkin, Jim Williams
Xilinx DS249 LogiCORE IP CORDIC v4.0, Data Sheet,
Xilinx, Inc.