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带温度补偿的扩频振荡器研究与设计

带温度补偿的扩频振荡器研究与设计

MIPI高速数据接口的研究与实现

MIPI高速数据接口的研究与实现

SystemVerilog 验证方法学 - Verification Methodology Manual for SystemVerilog

SystemVerilog 验证方法学 - Verification Methodology Manual for SystemVerilog

Janick Bergeron & Eduard Cemy & Alan Hunter & Andrew Nightingale 著 & 夏宇闻译

基于功耗优化的Pipelined+ADC系统结构设计与关键单元研究 (1)

基于功耗优化的Pipelined+[..] (1)

Analysis and Design of CMOS Clocking Circuits for Low Phase Noise

Analysis and Design of CMOS Clocking Circuits for Low Phase ...

Woorham Bae & Deog-Kyoon Jeong

Phillip E. Allen-CMOS Analog Circuit Design

Phillip E. Allen-CMOS Analog Circuit Design

Internal and external op-amp compensation: a control-centric tutorial - American Control Conference, 2004. Proceedings of the 2004

Internal and external op-amp compensation: a control-centric ...

Session 5: Analog Interfaces

Session 5: Analog Interfaces

A Low Power Two Stages CMOS OpAmp

A Low Power Two Stages CMOS OpAmp

Harmonic balance finite element method applications in nonlinear electromagnetics and power systems (Lu, Junwei Yamada, Sotoshi Zhao, Xiaojun) (z-lib.org)

Harmonic balance finite element method applications in nonlinear ...

tcsii.2005.A new modeling and optimization of gain-boosted cascode amplifier for high-speed and low-voltage applications

tcsii.2005.A new modeling and optimization of gain-boosted cascode ...

Sigma-Delta Converters Practical Design Guide, 2nd Edition

Sigma-Delta Converters Practical Design Guide, 2nd Edition

IEEE Standard for Information Technology—Telecommunications and information exchange between systems—LANs and MANs—Specific requirements—Part 11: WLAN MAC and PHY Specifications—Amendment 5: Enhancements for Higher Throughput

IEEE Standard for Information Technology—Teleco[..] and information ...

LAN/MAN Standards Committee of the IEEE Computer Society

Vivado Design Suite User Guide: Logic Simulation (UG900)

Vivado Design Suite User Guide: Logic Simulation (UG900)

架构艺术

架构艺术

未命名图书

未命名图书

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP Product Guide (PG055)

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...

Analysis and design of monolithic, high PSR, linear regulators for SoC applications - SOC Conference, 2004. Proceedings. IEEE International

Analysis and design of monolithic, high PSR, linear regulators ...

Category: This core implements a JESD204B interface supporting a line rate of up to 12.5 Gb/s on 1- 12 lanes using GTX or GTH transceivers in Zynq-7000 AP SoC devices

JESD204 v7.2 LogiCORE IP Product Guide (PG066)

JESD204 v7.2 LogiCORE IP Product Guide (PG066)