模拟电路设计——鲁棒性设计、Sig[..] (模拟电路设计——鲁棒性设计、Si[..] (z-lib.org)
作者
NONE
TOM
TMTT 202212
未知
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...
D.J. Foley;M.P. Flynn
EESM692
Prof. Alex Leung
无线通信的MATLAB和FPGA实现
西瑞克斯（北京）通信设备有限公司 编著
射频设计中的层次化建模
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wumin
Fundamentals of Digital Logic with Verilog Design, THIRD EDITION
Stephen Brown & Zvonko Vranesic
Session 36
Spectre Circuit Simulator RF Analysis Theory
Inc. Cadence Design Sys tems
openofdm-readthed[..]
Session 19: Optical Systems for Emerging Applications
PCI.Express.Base.2.0
HarmonicBalance
PHASE-INTERPOLATOR BASED PLL FREQUENCY SYNTHESIZER
Session 4: Processors
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何乐年
AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)
Xilinx, Inc.