VLSI Physical Design: From Graph Partitioning to Timing Closure
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Session 31: Analog Techniques
未知
最优控制理论与应用
CN201887731U-可修调的[..] 振荡电路
Modeling Jitter in PLL-based Frequency Synthesizers
Ken Kundert
射频系统内低中频滤波器的设计和研究
RF Matching Workshop
XU,YUE (K-China,ex1)
计算电磁学 by 王秉中,邵维 (z-lib.org)
CNKI
一种基于斩波调制的低压高精度CMO[..] 刘帘曦
Cadence Physical Verifi cation User Guide
Inc. Cadence Design Sys tems
自动控制原理
普林斯顿概率论读本 (史蒂文．J．米勒 (Steven J. Miller)) (Z-Library)
Verification of SD/MMC Controller IP Using UVM
一种应用于MCU待机模式的超低功耗[..]
Sahrling M. Analog Circuit Simulators for Integrated Circuit ...
2014 PhD-Thesis BAG A Designer-Oriented Framework for the Development ...
ISSCC2021-SC2
Low power and low voltage chopper amplifier without LPF
Layout Techniques for Integrated Circuit Designers
Sahrling
New developments in IC voltage regulators
R.J. Widlar
Analysis and Design of ESD Protection for Robust Low-Power Pierce ...
Kim B. Ostman & Erlend Strandvik & Phil Corbishley & Tor Oyvind Vedal & Mika Salmi