Middlebrook Part 2
mwidmer
Cadence SKILL Lan guage Reference
Inc. Cadence Design Sys tems
《ModelSim电子系统分析及仿真》
未知
Session 17
FPGA 全芯片 ESD 防护设计和优化
USER
Session 27
Analysis and Design of CMOS Clocking Circuits for Low Phase ...
Woorham Bae & Deog-Kyoon Jeong
Fundamental Principles Behind the Sigma-Delta ADC Topology Part ...
Michael Clifford & Analog Devices Inc
ISSCC2021-T6-Basics of DAC-based Wireline Transmitters
AMBA AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite ...
ARM Limited
基于功耗优化的Pipelined+[..] (1)
Noise and Spurious Tones Management Techniques for Multi-GHz ...
Adrian Maxim
finite elemennt anlysis in ansys
kubik
Practical RF Circuit Design for Modern Wireless Systems_ Passive ...
Name
bingdian001.com
Designing Control Loops for Linear and Switching Power Supplies: ...
Basso
集成电路原理与设计 教材
开关电容电路 从入门到精通
Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller ...
Shih-An Yu & Peter R. Kinget
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop ...
Yongsun Lee & Taeho Seong & Seyeon Yoo & Jaehyouk Choi
A 76 dB 1.7 GHz 0.18 m CMOS Tunable TIA Using Broadband Current ...
Hossein Miri Lavasani & Wanling Pan & Brandon Harrington & Reza Abdolvand & Farrokh Ayazi
Scaling <formula formulatype="inli[..] Notation="TeX">$L[..] ...
Noise and Spur Comparison of Delta-Sigma Modulators in Fractional-N ...
Bo Zhou & Yao Li & Fuyuan Zhao