A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
ISSCC2021-1 3
未知
thesis.dvi
THE DESIGN OF MASTER-SLAVE DLL FOR DDR2 SDRAM CONTROLLER IN ...
iccad095
Electronic Circuit and System Simulation Methods
Lawrence T. Pillage, Ronald A. Rohrer, Chandramouli Visweswariah
Striving for small-signal stability - IEEE Circuits and Devices ...
IEEE
Sigma-Delta Converters. Practical Design Guide (José M. de la ...
Signals Systems (Alan V. Oppenheim, Alan S. Willsky etc.) (Z-Library)
Session 9: ML Processors From Cloud to Edge
多采样率系统:采样率转换和数字滤波器组
基于全反馈的高稳定性LDO线性稳压器
工程电路分析
mssc.2015.Razavi-The StrongARM Latch
ISSCC2021-SC3-Clo[..] Clock Distribution, and Clock Management ...
CMOS Analog Circuit Design (1)
PID Controllers 2nd Edition KarlJ. Astrom
C++ Primer Plus(第6版)中文版
[美] Stephen Prata
基于LDO新型过流保护电路设计
A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm ...
Kuan-Yueh Shen & Syed Feruz Syed Farooq & Yongping Fan & Khoa Minh Nguyen & Qi Wang & Mark L. Neidengard & Nasser Kurd & Amr Elshazly