Design and Simulation of LNA using Advanced Design Systems (ADS)
USER
The Problem of PLL Power Consumption
Behzad Razavi
Computational electromagnetism variational formulations, complementarity, ...
未知
93.张强-高性能Rail to Rail恒定跨导CMOS运算放大器
VerilogA系统设计与仿真（可[..]
High-Speed Architecture for a Programmable Frequency Divider ...
IEEE
深入理解linux内核(第三版)
通信原理 第7版
樊昌信，曹丽娜编著
CN106656160A-上海集成[..]
Bandgap & LDO-李福乐
Administrator
Design of Analog CMOS Integrated Circuits
Razavi
SystemVerilog验证 测试平台编写指南
Spectre Circuit Simulator and Accelerated Parallel Simula tor ...
Inc. Cadence Design Sys tems
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ...
Chun-Cheng Liu;Soon-Jyh Chang;Guan-Ying Huang;Ying-Zu Lin
Session 5
High Performance SAR-based ADC Design in Deep Sub-micron CMOS
lei sun
A low-power small-area /spl plusmn/7.28-ps-ji[..] 1-GHz DLL-based ...
Chulwoo Kim & In-Chul Hwang & Sung-Mo Kang
LDO中过温保护电路的设计
Enhanced phase noise modeling of fractional-N frequency synthesizers
H. Arora;N. Klemmer;J.C. Morizio;P.D. Wolf