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一种带软启动电路的带隙基准电压源的实现张科

一种带软启动电路的带隙基准电压源的实现张科

高速高精度ADC中基准电压源的研究与设计 (1)

高速高精度ADC中基准电压源的研究与设计 (1)

S_Para_E.PM6

S_Para_E.PM6

LDO设计论文

LDO设计论文

Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs

Embedded Mixed-Signal IP Development Methodology in 90nm CMOS ...

Rakesh H. Patel & William Bereza

数值分析

数值分析

抗浪涌静电器件防护机理与片上集成实验研究

抗浪涌静电器件防护机理与片上集成实验研究

IP3 and Intermodulation Guide | Maxim Integrated

IP3 and Intermodulation Guide | Maxim Integrated

Frequency Compensation of Op-amp and its types Circuit Digest

Frequency Compensation of Op-amp and its types Circuit Digest

Session 19

Session 19

Universal Verification Methodology (UVM) Cookbook

Universal Verification Methodology (UVM) Cookbook

Functional Verification Methodology Team - Mentor & A Siemens Business

控制之美（卷1）——控制理论从传递函数到状态空间

控制之美（卷1）——控制理论从传递[..]

Session 22

Session 22

Gabriel Rincon-Mora - Analog IC Design with Low-Dropout Regulators (LDOs) (Electronic Engineering) (2009)

Gabriel Rincon-Mora - Analog IC Design with Low-Dropout Regulators ...

Analog IC Design & Low-Dropout Regulators (LDOs) (Electronic Engineering) (2009) ...

一种适用于DDR内存驱动的LDO芯片设计

一种适用于DDR内存驱动的LDO芯片设计

数值分析（第5版）习题解答 (李庆扬) (z-lib.org)

数值分析（第5版）习题解答 (李庆扬) (z-lib.org)

A precise on-chip voltage generator for a gigascale dram with a negative word-line scheme - Solid-State Circuits, IEEE Journal of

A precise on-chip voltage generator for a gigascale dram with ...

一种低静态电流、高稳定性的LDO线性稳压器

一种低静态电流、高稳定性的LDO线[..]

Category: IEEE Journal of Solid-State Circuits;2001;36;3;10.1109/4.910480

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...

D.J. Foley;M.P. Flynn