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一种高摆幅软启动线性稳压源设计

一种高摆幅软启动线性稳压源设计

Book.DVI

Book.DVI

Session 9

Session 9

高性能音频Delta-Sigma数据转换器的设计与优化技术研究

高性能音频Delta-Sigma数[..]

Wishbone B4

Wishbone B4

Spectre Circuit Simulator and Accelerated Parallel Simula tor RF Analysis in ADE Explorer User Guide

Spectre Circuit Simulator and Accelerated Parallel Simula tor ...

Inc. Cadence Design Sys tems

eetop.cn 电路分析

eetop.cn 电路分析

Analog Behavioral Modeling with the Verilog-A Language

Analog Behavioral Modeling with the Verilog-A Language

Razavi Analog CMOS

Razavi Analog CMOS

HFIC chapter 7 low-noise amplifier design

HFIC chapter 7 low-noise amplifier design

Continuous-Time Delta-Sigma Modulators for High-Speed AD Conversion Theory, Practice and Fundamental Performance Limits by James A. Cherry, W. Martin Snelgrove (auth.) (z-lib.org)

Continuous-Time Delta-Sigma Modulators for High-Speed AD Conversion ...

UVM实战（卷Ⅰ)

UVM实战（卷Ⅰ)

A 25Gb/s PAM4 Transmitter in 90nm CMOS SOI

A 25Gb/s PAM4 Transmitter in 90nm CMOS SOI

Design of Chopper-Stabilized Amplifiers With Reduced Offset for Sensor Applications

Design of Chopper-Stabilized Amplifiers With Reduced Offset ...

自动控制原理

自动控制原理

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Ying-Zu Lin & Chung-Ming Huang & Chih-Hao Huang & Linkai Bu & Chih-Chung Tsai

ISM-PLL

ISM-PLL

ofdm功能说明文档

ofdm功能说明文档

Category: IEEE Journal of Solid-State Circuits;2001;36;3;10.1109/4.910480

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...

D.J. Foley;M.P. Flynn