93.张强-高性能Rail to Rail恒定跨导CMOS运算放大器
未知
ISSCC2021-SC1-Int[..] to PLLs Phase Noise, Modeling, and Key ...
Session 33
信号与系统下 第三版
SystemVerilog 验证方法学 - Verification Methodology Manual for SystemVerilog
Janick Bergeron & Eduard Cemy & Alan Hunter & Andrew Nightingale 著 & 夏宇闻 译
开关电容电路 从入门到精通
Switching Power Supplies A to Z
Maniktala, Sanjaya.
Understanding Jitter and Phase Noise : A Circuits and Systems ...
Nicola Da Dalt; Ali Sheikholeslami & Ali Sheikholeslami
ADS2008射频电路设计与仿真实例
徐兴福 著
集成电路版图设计 [陆学斌 主编] 2012年版
一种应用于DC DC转换器的自举电路设计
Amplifiers, Comparators, Multipliers, Filters, and Oscillators; ...
Tertulien Ndjountche
纳米级CMOS逐次逼近A D转换器设计研究与实现
lnaDesign4
Raed Abd-Alhameed
Session 19
Session 25: DRAM
Low-Jitter Process-Independent DLL and PLL Based on Self-Biased ...
IEEE
A modeling approach for /spl Sigma/-/spl Delta/ fractional-N ...
M.H. Perrott & M.D. Trott & C.G. Sodini
Truly Nonlinear Oscillations: Harmonic Balance, Parameter Expansions, ...
Ronald E. Mickens