A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with ...
IEEE
芯片漫游指南
未知
LDO LINEAR REGULATOR WITH IMPROVED TRANSIENT RESPONSE
Analysis and design of monolithic, high PSR, linear regulators ...
研究生系列教材 数字信号处理:时域离散随机信号处理 11761429
DDS信号发生器的实现
Administrator
A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process
Wenzha Yang & Yi Zhang & Enwen Dai & ZhiLin Feng & Wei Li
Next-Generation ADCs, High-Performance Power Management, and ...
Sampled Systems and the Effects of Clock Phase Noise and Jitter ...
Analog Devices, Inc.
Report for current mirror OPAMP
逐达逼近型模数转换器的低功耗与高速[..]
Distributed MOS varactor biasing for VCO gain equalization in ...
J. Mira & T. Divel & S. Ramet & J.-B. Begueret & Y. Deval
计算电磁学要论 by 盛新庆 (z-lib.org)
CNKI
低压高速LDO电路系统的分析与设计
模拟电路版图的艺术
ALAN HASTINGS著
Understanding Delta-Sigma Data Converters 2nd edition
SHANTHI PAVAN, RICHARD SCHREIER & GABOR C. TEMES
jrproc.1950.Bothw[..] F.E.-Nyquist Diagrams and the Routh-Hurwitz ...
AD9635 cn
Design techniques for cascoded CMOS op amps with improved PSRR ...
D.B. Ribner & M.A. Copeland