PHASE ERROR CANCELLATION
未知
CMOS Analog Circuit Design
4<8=8AB@0B>@
凸优化 BoydVandenberghe 中文完整版 (Boyd Vandenberghe) (Z-Library)
通信标准对数据转换器的要求V1.0
Relationship between frequency response and settling time of ...
B.Y.T. Kamath, R.G. Meyer & P.R. Gray
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...
D.J. Foley;M.P. Flynn
TI-CICC2006-A Sub-i V Low-Noise Bandgap Voltage Reference
计算电磁学要论 by 盛新庆 (z-lib.org)
CNKI
THE DESIGN OF MASTER-SLAVE DLL FOR DDR2 SDRAM CONTROLLER IN ...
iccad095
ch3_pnjunction
Claudio Talarico
Abraham uta GPIO ESD
Administrator
Electronics Explained
Frenzel, Louis E.
《Linux从初学到精通》.(张勤[..]
自动控制理论中的根轨迹法 (（苏）Э.Γ.乌杰尔曼著；孙吴译) (Z-Library)
25Gbps系统封装和高速互连的信[..]
Session 21
INTRODUCTION TO NUMERICAL PROGRAMMING: A Practical Guide for ...
Beu, Titus, Adrien
CMOS模拟集成电路设计与仿真实例 基于Hspice
A 470-nA Quiescent Current and 92.7%/94.7[..] Efficiency ...