理工书库 lilin | Category: 2010 IEEE International Solid-State Circuits Conference - (ISSCC);2010; ; ;10.1109/ISSCC.2010.5433970

Discover (Random Books)

半导体器件物理(第3版)-中文版-施敏-高清版

半导体器件物理(第3版)-中文版-[..]

一种快速瞬态响应无片外电容LDO

一种快速瞬态响应无片外电容LDO

Spectre Circuit Simulator Components and Device Models Reference

Spectre Circuit Simulator Components and Device Models Reference

Inc. Cadence Design Sys tems

CMOS射频集成电路设计(第二版) —— The Design of CMOS Radio-Frequency Integrated Circuits, Second Edition

CMOS射频集成电路设计(第二版) —— The Design of CMOS Radio-Frequency Integrated ...

美 & Thomas H. Lee 著 & 余志平周润德等译

StarRC User Guide and Command Reference

StarRC User Guide and Command Reference

Session 6

Session 6

Static timing analysis for nanometer designs a practical approach (Rakesh Chadha, J. Bhasker (auth.)) (z-lib.org)

Static timing analysis for nanometer designs a practical approach ...

硅基压控振荡器的研究与设计电子科技大学彭羽

硅基压控振荡器的研究与设计电子科技大学彭羽

Herbst-MIT2011--A Low-Noise Bandgap Voltage Reference Employing Dynamic Element Matching

Herbst-MIT2011--A Low-Noise Bandgap Voltage Reference Employing ...

Session 24: Advanced Embedded Memories

Session 24: Advanced Embedded Memories

A simple three-terminal IC bandgap reference

A simple three-terminal IC bandgap reference

SKILL Development of Parameterized Cells 5141

SKILL Development of Parameterized Cells 5141

IEEE Std 802.11b-1999

IEEE Std 802.11b-1999

零点极点

零点极点

fluids-04-00159-v2

fluids-04-00159-v2

Understanding Jitter Requirements of PLL-Based Processors Application Note (EE-261)

Understanding Jitter Requirements of PLL-Based Processors Application ...

ANALOG DEVICES INC.

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...

D.J. Foley;M.P. Flynn

AMBA 3 APB Protocol Specification

AMBA 3 APB Protocol Specification

Category: 2010 IEEE International Solid-State Circuits Conference - (ISSCC);2010; ; ;10.1109/ISSCC.2010.5433970

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Ying-Zu Lin & Chung-Ming Huang & Chih-Hao Huang & Linkai Bu & Chih-Chung Tsai