Robust Design of LV/LP Low-Distortion CMOS Rail-to-Rail Input ...
未知
A 470-nA Quiescent Current and 92.7%/94.7[..] Efficiency ...
Gray Hurst Analysis and Design of Analog Integra
模拟IC 艾伦答案
Session 31: Analog Techniques
Microsoft Word - CummingsSNUG2008B[..]
cliffc
模拟CMOS集成电路设计 第一版
基于自偏置技术的锁相环设计 刘克赛2019
刘克赛
基于功耗优化的Pipelined+[..] (1)
2004Beek
模拟CMOS集成电路设计（拉扎维）答案
陈鹏远
Session 30: Non-Volatile Memories
man.book
merickso
一种高摆率低功耗无片外电容的LDO设计
A fast-settling CMOS op amp for SC circuits with 90-dB DC gain
K. Bult;G.J.G.M. Geelen
CMOS带隙电压基准的误差及其改进 陈浩琼
introduction.ppt
kdjwang
SPI Block Guide V4
Freescale Semiconductor, Inc.
Analysis and Design of ESD Protection for Robust Low-Power Pierce ...
Kim B. Ostman & Erlend Strandvik & Phil Corbishley & Tor Oyvind Vedal & Mika Salmi