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通信系统中的多采样率信号处理

通信系统中的多采样率信号处理

锁相环(PLL)电路设计与应用

锁相环(PLL)电路设计与应用

(日)远坂俊昭著何希才译

LDO设计小结二

LDO设计小结二

Gabriel Rincon-Mora - Analog IC Design with Low-Dropout Regulators (LDOs) (Electronic Engineering) (2009)

Gabriel Rincon-Mora - Analog IC Design with Low-Dropout Regulators ...

Analog IC Design & Low-Dropout Regulators (LDOs) (Electronic Engineering) (2009) ...

Kendall Su, Analog Filters, 2nd Ed.

Kendall Su, Analog Filters, 2nd Ed.

eetop.cn Matching

eetop.cn Matching

TEMPERATURE AND PROCESS (56) COMPENSATED CURRENT REFERENCE CIRCUITS

TEMPERATURE AND PROCESS (56) COMPENSATED CURRENT REFERENCE CIRCUITS

数据转换器

数据转换器

AMBA AXI Protocol Specification

AMBA AXI Protocol Specification

低压低功耗CMOS带隙电压基准及启动电路设计许长喜

低压低功耗CMOS带隙电压基准及启[..] 许长喜

数值分析.Timothy Sauer.图灵中文扫描版

数值分析.Timothy Sauer.图灵中文扫描版

LDO低输出噪声的分析与优化设计朱勤为

LDO低输出噪声的分析与优化设计朱勤为

A simple three-terminal IC bandgap reference

A simple three-terminal IC bandgap reference

PlanarSpiralInductors,PlanarAntennasandEmbeddedPlanarTransformers

PlanarSpiralInduc[..]

Calibre® DESIGNrev Reference Manual

Calibre® DESIGNrev Reference Manual

Siemens Industry Software

CMOS带隙电压基准的误差及其改进陈浩琼

CMOS带隙电压基准的误差及其改进陈浩琼

man_mentor_vip_axi4lite_ae_usr.book

man_mentor_vip_ax[..]

lnaDesign4

lnaDesign4

Raed Abd-Alhameed

Category: using a fraction of the resources of the fully featured AXI Memory Mapped to PCIe Gen2 bridge.

7 Series FPGAs Gen2 Integrated Block for PCIe to AXI4-Lite Bridge (XAPP1286)

7 Series FPGAs Gen2 Integrated Block for PCIe to AXI4-Lite Bridge ...