锁相环(PLL)电路设计与应用
(日)远坂俊昭 著 何希才译
CMOS Analog Circuit Design (1)
未知
finite elemennt anlysis in ansys
kubik
The advanced part of A treatise on the dynamics of a system ...
Routh, Edward John, 1831-1907.
Sampled Systems and the Effects of Clock Phase Noise and Jitter ...
Analog Devices, Inc.
一种低静态电流、高稳定性的LDO线[..]
微带电路——清华
Radio Frequency Integrated Circuits and Systems
Hooman Darabi
微积分学教程 三卷合一 (菲赫金哥尔茨) (Z-Library)
Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller ...
Shih-An Yu & Peter R. Kinget
A 1.24 μA Quiescent Current NMOS Low Dropout Regulator With ...
Raveesh Magod & Bertan Bakkaloglu & Sanjeev Manandhar
A0130105
Preeti Sharma
Global Optimization Toolbox User's Guide
The MathWorks, Inc.
ISSCC2021-T11-Ult[..] Power Wireless Receiver Design
Distributed MOS varactor biasing for VCO gain equalization in ...
J. Mira & T. Divel & S. Ramet & J.-B. Begueret & Y. Deval
Robust Control Design with MATLAB® (Da-Wei Gu PhD, DIC, CEng ...
4<8=8AB@0B>@
反馈运算放大器电路的噪声分析和设计
esd-circuits-and-[..]
7 Series FPGAs Gen2 Integrated Block for PCIe to AXI4-Lite Bridge ...
Xilinx, Inc.