模拟CMOS集成电路设计第一版
未知
VLSI Physical Design: From Graph Partitioning to Timing Closure
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
SAR ADC-MIT
Session 19
CMOS模拟集成电路
王永生
无线通信中的射频收发系统设计（英文版）
VerilogA系统设计与仿真（可[..]
Nested Miller compensation in low-power CMOS design
Ka Nang Leung;P.K.T. Mok
Pieter Harpe, Andrea Baschirotto, Kofi A. A. Makinwa eds. High-Performance ...
基于XILINX FPGA的OFDM通信系统基带设计
Fundamentals of Digital Logic with Verilog Design, THIRD EDITION
Stephen Brown & Zvonko Vranesic
Modified modeling of Miller compensation for two-stage operational ...
H.C. Yang;D.J. Allstot
AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...
Xilinx, Inc.
HJ-MASH 多模多标准CMOS锁相环频率综合器[..] 史鹏鹏
Jish
Understanding Jitter Requirements of PLL-Based Processors Application ...
ANALOG DEVICES INC.
共源共栅实验五
USER
A mixed-mode esd protection circuit simulation-design methodology ...
Session 5
FinFET Devices for VLSI Circuits and Systems
Samar K. Saha