理工书库 lilin | Category: 页码：304

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Triple-Speed Ethernet Intel® FPGA IP User Guide

Triple-Speed Ethernet Intel® FPGA IP User Guide

Intel Corporation

线性代数及其应用（第5版－Gilbert Strang

线性代数及其应用（第5版－Gilbert Strang

ADS应用详解：射频电路设计与仿真

ADS应用详解：射频电路设计与仿真

陈艳华，李朝晖，夏玮编著

Microsoft Word - translator_preface.doc

Microsoft Word - translator_prefac[..]

Physical design essentials an ASIC design implementation perspective (Khosrow Golshan) (z-lib.org)

Physical design essentials an ASIC design implementation perspective ...

ISSCC2021 Session 17

ISSCC2021 Session 17

深入理解LINUX虚拟内存管理

深入理解LINUX虚拟内存管理

（爱尔兰）MEL GORMAN著

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...

D.J. Foley;M.P. Flynn

高等数学第7版上

高等数学第7版上

同济大学数学系编

CMOS Circuit Design, Layout, and Simulation, 3rd Edition (IEEE Press Series on Microelectronic Systems)

CMOS Circuit Design, Layout, and Simulation, 3rd Edition (IEEE ...

IEEE Std 802.11b-1999

IEEE Std 802.11b-1999

控制之美卷1 (王天威) (Z-Library)

控制之美卷1 (王天威) (Z-Library)

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Microsoft Word - RFKitDoc_v1 3.doc

Microsoft Word - RFKitDoc_v1 3.doc

Dynamic Response of Linear Systems Impact of Pole & Zero Locations

Dynamic Response of Linear Systems Impact of Pole & Zero Locations

PlanarSpiralInductors,PlanarAntennasandEmbeddedPlanarTransformers

PlanarSpiralInduc[..]

Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level

Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture ...

USB 3 1 r1.0

USB 3 1 r1.0

Category: 页码：304

ANALOG CMOS IC DESIGN 模拟CMOS集成电路设计

ANALOG CMOS IC DESIGN 模拟CMOS集成电路设计

魏廷存 & 陈莹梅 & 胡正飞