ISSCC2020-01 Visuals
Steve Bonney
A compact power-efficient 3 V CMOS rail-to-rail input/output ...
IEEE
高等数学 第7版 上
同济大学数学系编
Session 17: DC-DC Converters
未知
Virtuoso Editing 的使用简介
Richey
Session 6: High-Performance Receivers and Transmitters for Sub-6GHz ...
24位96KSPSΣ-Δ调制器的设计
CBJ
RISC-V IOMMU Architecture Specification
IOMMU Task Group
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop ...
Yongsun Lee & Taeho Seong & Seyeon Yoo & Jaehyouk Choi
Design Optimization of Power and Area of Two-Stage CMOS Operational ...
Telugu Maddileti;Govindarajulu Salendra;Chandra Mohan Reddy ...
IEEE Std 1801™-2018, IEEE Standard for Design and Verification ...
Design Automation Standards Committee of the IEEE Computer Society
PLL Perfomance, Simulation, and Design
Dean Banerjee
开关电容电路 从入门到精通
开关电容电路 从入门到精通 -刘明亮
A Low Power Two Stages CMOS OpAmp
Session 14: mm-Wave Transceivers for Communication and Radar
Session 1: Plenary Session — Invited Papers
一种具有温度补偿 高电源抑制比的带隙基准源 何捷 (1)
Xilinx DS534, FIR Compiler v5.0, Data Sheet
Xilinx, Inc.