Session 1: Plenary Session — Invited Papers
未知
Scaling <formula formulatype="inli[..] Notation="TeX">$L[..] ...
Shih-An Yu & Peter R. Kinget
Tempus User Guide
Inc. Cadence Design Sys tems
Next-Generation ADCs, High-Performance Power Management, and ...
Session 12
A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm ...
Kuan-Yueh Shen & Syed Feruz Syed Farooq & Yongping Fan & Khoa Minh Nguyen & Qi Wang & Mark L. Neidengard & Nasser Kurd & Amr Elshazly
ADS2011射频电路设计与仿真实例
徐兴福著
低功耗CMOS逐次逼近型模数转换器 [朱樟明，杨银堂著][科学出版社][..]
Electromagnetics for High-speed Analog and Digital Communication ...
Ali M. Niknejad
js.2010.PFD biased with shunt regulator
SKILL Development of Parameterized Cells 5141
ldmos tech
分段温度曲率补偿双极工艺带隙基准设计
Nios II Processor Reference Guide
Intel Corporation
LDO与VLDO的设计原理及性能测试
Using the Python API to Develop Process Portable PyCells
Inc. Synopsys
Microsoft Word - translator_prefac[..]
Zhiping Yu
Electronic Circuit and System Simulation Methods
Lawrence T. Pillage, Ronald A. Rohrer, Chandramouli Visweswariah
AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...
Xilinx, Inc.
AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)
JESD204 v7.2 LogiCORE IP Product Guide (PG066)
Xilinx PG153 LogiCORE IP AXI Quad Serial Peripheral Interface ...
Xilinx DS534, FIR Compiler v5.0, Data Sheet
Xilinx DS558, LogiCORE IP DDS Compiler v4.0, Data Sheet