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Book.DVI

射频微电子学

射频微电子学

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ...

Chun-Cheng Liu;Soon-Jyh Chang;Guan-Ying Huang;Ying-Zu Lin

开关电源设计第3版

开关电源设计第3版

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12位50Msps流水线A D转换器的研究与设计

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DDS信号发生器的实现

DDS信号发生器的实现

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CH01

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Session 19: Optical Systems for Emerging Applications

LDO与VLDO的设计原理及性能测试

LDO与VLDO的设计原理及性能测试

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LDO设计小结一

Instruction for Camera-Ready Paper

Instruction for Camera-Ready Paper

A TIA in CMOS 0.18um

A TIA in CMOS 0.18um

基于Latch的CMOS动态比较器的研究

基于Latch的CMOS动态比较器的研究

GmID Methodology

GmID Methodology

Constraining Designs for Synthesis and Timing Analysis A Practical Guide to Synopsys Design Constraints (SDC) (Sridhar Gangadharan, Sanjay Churiwala (auth.)) (z-lib.org)

Constraining Designs for Synthesis and Timing Analysis A Practical ...

CMOS模拟集成电路设计与仿真实例-基于Cadence ADE

CMOS模拟集成电路设计与仿真实例[..] ADE

$Wideband RF PLL fractional/integer frequency synthesizer with integrated VCOs and LDOs$

Wideband RF PLL fractional/integer frequency synthesizer with ...

STMICROELECTRONICS

Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller Area But With Constant Performance

Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller ...

Shih-An Yu & Peter R. Kinget

Category: The Xilinx LogiCORE IP CORDIC core implements a generalized coordinate rotational digital computer (CORDIC) algorithm.

Xilinx DS249 LogiCORE IP CORDIC v4.0, Data Sheet,

Xilinx DS249 LogiCORE IP CORDIC v4.0, Data Sheet,