Cadence PVS Developers Guide
Inc. Cadence Design Sys tems
《自动控制原理》[卢京潮 编著]
未知
AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...
Xilinx, Inc.
Standard Verification Rule Format (SVRF) Manual 2020
Mentor Graphics Corporation
A comparative study of various current mirror configurations_ ...
Bhawna Aggarwal & Maneesha Gupta & A.K. Gupta
PLL频率合成器的杂散性能分析
HFSS电磁仿真设计从入门到精通
未命名图书
射频接收机中模拟信道滤波器设计
Session 12: Innovations in Low-Power and Secure IoT
A fast-settling CMOS op amp for SC circuits with 90-dB DC gain
K. Bult;G.J.G.M. Geelen
NONE
TOM
模拟电路与数字电路
林捷
Artificial Intelligence: A Modern Approach, Global Edition, ...
Stuart Russell / Peter Norvig
PrimeWave� Design Environment for Reliability Analysis User ...
Inc. Synopsys
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...
D.J. Foley;M.P. Flynn
基于延迟锁相环的时钟发生器设计
Advanced Techniques in RF Power Amplifier Design (Ripped by ...
Xilinx PG153 LogiCORE IP AXI Quad Serial Peripheral Interface ...
Creating Qsys Components
Altera Corporation